/*
 * Copyright (c) 2009-2010 HIT Microelectronic Center
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *
 * Authors: Gou Pengfei
 *          Jin Yinghan
 *
 * Date:    Dec. 2009
 *
 */

#include <limits>
#include <vector>

#include "cpu/edge/fu_pool.hh"
#include "cpu/edge/inst_queue.hh"
#include "enums/OpClass.hh"
#include "params/DerivEdgeCPU.hh"
#include "sim/core.hh"
#include "base/bitfield.hh"

using namespace std;

template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
    int fu_idx, InstructionQueue<Impl> *iq_ptr)
    : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr),
      freeFU(false)
{
    this->setFlags(Event::AutoDelete);
}

template <class Impl>
void
InstructionQueue<Impl>::FUCompletion::process()
{
    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
    inst = NULL;
}


template <class Impl>
const char *
InstructionQueue<Impl>::FUCompletion::description() const
{
    return "Functional unit completion";
}

template <class Impl>
InstructionQueue<Impl>::InstructionQueue(CPU *cpu_ptr,  Execute* execute, DerivEdgeCPUParams *params)
    : cpu(cpu_ptr),
      executeStage(execute),
      fuPool(params->fuPool),
      numEntries(params->numIQEntries),
      totalWidth(params->issueWidth),
      numPhysIntRegs(params->numPhysIntRegs),
      numPhysFloatRegs(params->numPhysFloatRegs),
      commitToExecuteDelay(params->commitToExecuteDelay),
      isPerfectPredication(false)
{
    assert(totalWidth <= Impl::MaxIssueWidth);

    assert(fuPool);

    switchedOut = false;

    numThreads = params->numThreads;

    // Set the number of physical registers as the number of int + float
    numPhysRegs = numPhysIntRegs + numPhysFloatRegs;

    // Set register dependence graph
    regDepGraph.resize(numPhysRegs);
    regDepGraph.setInstQueuePtr(this);

    //Initialize Mem Dependence Units
    for (ThreadID tid = 0; tid < numThreads; tid++) {
        memDepUnit[tid].init(params, tid);
        memDepUnit[tid].setIQ(this);

        for (int i = 0; i < Impl::MaxFrameNum; i++) {
            instQueue[tid][i].resize(TheISA::MaxInstsInBlock);
            readQueue[tid][i].resize(TheISA::HeaderSize);
            writeQueue[tid][i].resize(TheISA::HeaderSize);

            // Initialize this record to 0
            frameRecordBoard[tid][i] = 0;
        }
    }

    resetState();

    std::string policy = params->smtIQPolicy;

    //Convert string to lowercase
    std::transform(policy.begin(), policy.end(), policy.begin(),
                   (int(*)(int)) tolower);

    //Figure out resource sharing policy
    if (policy == "dynamic") {
        iqPolicy = Dynamic;

        //Set Max Entries to Total ROB Capacity
        for (ThreadID tid = 0; tid < numThreads; tid++) {
           maxEntries[tid] = numEntries;
        }

    } else if (policy == "partitioned") {
        iqPolicy = Partitioned;

        //@todo:make work if part_amt doesnt divide evenly.
        int part_amt = numEntries / numThreads;

        //Divide ROB up evenly
        for (ThreadID tid = 0; tid < numThreads; tid++) {
            maxEntries[tid] = part_amt;
        }

        DPRINTF(EdgeIQ, "EdgeIQ sharing policy set to Partitioned:"
                "%i entries per thread.\n",part_amt);
    } else if (policy == "threshold") {
        iqPolicy = Threshold;

        double threshold =  (double)params->smtIQThreshold / 100;

        int thresholdIQ = (int)((double)threshold * numEntries);

        //Divide up by threshold amount
        for (ThreadID tid = 0; tid < numThreads; tid++) {
            maxEntries[tid] = thresholdIQ;
        }

        DPRINTF(EdgeIQ, "EdgeIQ sharing policy set to Threshold:"
                "%i entries per thread.\n",thresholdIQ);
    } else {
       assert(0 && "Invalid EdgeIQ Sharing Policy.Options Are:{Dynamic,"
              "Partitioned, Threshold}");
    }

    if (params->predicationMode == "Perfect") {
        if (!params->preExecuteMode) {
            fatal("Perfect predication should work with preExecuteMode.\n");
        }

        isPerfectPredication = true;
    }
}

template <class Impl>
InstructionQueue<Impl>::~InstructionQueue()
{
    regDepGraph.reset();
#ifdef DEBUG
    cprintf("Nodes traversed: %i, removed: %i\n",
            regDepGraph.nodesTraversed, regDepGraph.nodesRemoved);
#endif
}

template <class Impl>
std::string
InstructionQueue<Impl>::name() const
{
    return cpu->name() + ".iq";
}

template <class Impl>
void
InstructionQueue<Impl>::regStats()
{
    using namespace Stats;
    iqInstsAdded
        .name(name() + ".iqInstsAdded")
        .desc("Number of instructions added to the IQ ")
        .prereq(iqInstsAdded);

    iqReadsAdded
        .name(name() + ".iqReadsAdded")
        .desc("Number of reads added to the IQ ")
        .prereq(iqReadsAdded);

    iqWritesAdded
        .name(name() + ".iqWritesAdded")
        .desc("Number of writes added to the IQ ")
        .prereq(iqWritesAdded);

    iqInstsIssued
        .name(name() + ".iqInstsIssued")
        .desc("Number of instructions issued")
        .prereq(iqInstsIssued);

    iqIntInstsIssued
        .name(name() + ".iqIntInstsIssued")
        .desc("Number of integer instructions issued")
        .prereq(iqIntInstsIssued);

    iqFloatInstsIssued
        .name(name() + ".iqFloatInstsIssued")
        .desc("Number of float instructions issued")
        .prereq(iqFloatInstsIssued);

    iqBranchInstsIssued
        .name(name() + ".iqBranchInstsIssued")
        .desc("Number of branch instructions issued")
        .prereq(iqBranchInstsIssued);

    iqMemInstsIssued
        .name(name() + ".iqMemInstsIssued")
        .desc("Number of memory instructions issued")
        .prereq(iqMemInstsIssued);

    iqMiscInstsIssued
        .name(name() + ".iqMiscInstsIssued")
        .desc("Number of miscellaneous instructions issued")
        .prereq(iqMiscInstsIssued);

    iqDummyInstsIssued
        .name(name() + ".iqDummyInstsIssued")
        .desc("Number of squashed or block competed instructions issued")
        .prereq(iqDummyInstsIssued);

    iqInstsSquashed
        .name(name() + ".iqInstsSquashed")
        .desc("Number of squashed instructions.")
        .prereq(iqInstsSquashed);

    iqRegReadDep
        .name(name() + ".iqRegReadDep")
        .desc("Number of reg-reads dependent upon unexecuted reg-writes.")
        .prereq(iqRegReadDep);

    iqRegWriteWrited
        .name(name() + ".iqRegWriteWrited")
        .desc("Number of reg-writes really writed back.")
        .prereq(iqRegWriteWrited);

    iqOperandsPropagated
        .name(name() + ".iqOperandsPropagated")
        .desc("Number of operands propagated.")
        .prereq(iqOperandsPropagated);

    iqNullTokenPropagated
        .name(name() + ".iqNullTokenPropagated")
        .desc("Number of null token propagated.")
        .prereq(iqNullTokenPropagated);

    iqExceptTokenPropagated
        .name(name() + ".iqExceptTokenPropagated")
        .desc("Number of  except token propagated.")
        .prereq(iqExceptTokenPropagated);

    iqPredicationPropagated
        .name(name() + ".iqPredicationPropagated")
        .desc("Number of  predication propagated.")
        .prereq(iqPredicationPropagated);

    iqCorrectPredPredication
        .name(name() + ".iqCorrectPredPredication")
        .desc("Number of correctly predict predication.");

    numIssuedDist
        .init(0,totalWidth,1)
        .name(name() + ".ISSUE:issued_per_cycle")
        .desc("Number of insts issued each cycle")
        .flags(pdf)
        ;

    statIssuedInstType
        .init(numThreads,Enums::Num_OpClass)
        .name(name() + ".ISSUE:FU_type")
        .desc("Type of FU issued")
        .flags(total | pdf | dist)
        ;
    statIssuedInstType.ysubnames(Enums::OpClassStrings);

    issueRate
        .name(name() + ".ISSUE:rate")
        .desc("Inst issue rate")
        .flags(total)
        ;
    issueRate = iqInstsIssued / cpu->numCycles;

    statFuBusy
        .init(Num_OpClasses)
        .name(name() + ".ISSUE:fu_full")
        .desc("attempts to use FU when none available")
        .flags(pdf | dist)
        ;
    for (int i=0; i < Num_OpClasses; ++i) {
        statFuBusy.subname(i, Enums::OpClassStrings[i]);
    }

    fuBusy
        .init(numThreads)
        .name(name() + ".ISSUE:fu_busy_cnt")
        .desc("FU busy when requested")
        .flags(total)
        ;

    fuBusyRate
        .name(name() + ".ISSUE:fu_busy_rate")
        .desc("FU busy rate (busy events/executed inst)")
        .flags(total)
        ;
    fuBusyRate = fuBusy / iqInstsIssued;

    for (ThreadID tid = 0; tid < numThreads; tid++) {
        // Tell mem dependence unit to reg stats as well.
        memDepUnit[tid].regStats();
    }
}

template <class Impl>
void
InstructionQueue<Impl>::resetState()
{
    //Initialize thread IQ counts
    for (ThreadID tid = 0; tid <numThreads; tid++) {
        count[tid] = 0;
    }

    // Initialize the number of free IQ entries.
    freeEntries = numEntries;

    for (ThreadID tid = 0; tid < numThreads; ++tid) {
        squashedSeqNum[tid] = 0;
    }

    for (int i = 0; i < Num_OpClasses; ++i) {
        while (!readyInsts[i].empty())
            readyInsts[i].pop();
        queueOnList[i] = false;
        readyIt[i] = listOrder.end();
    }
    nonSpecInsts.clear();
    listOrder.clear();
}

template <class Impl>
void
InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
    activeThreads = at_ptr;
}

template <class Impl>
void
InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<Issue2Execute> *i2e_ptr)
{
    issueToExecuteQueue = i2e_ptr;
}

template <class Impl>
void
InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
    timeBuffer = tb_ptr;

    fromCommit = timeBuffer->getWire(-commitToExecuteDelay);
}

template <class Impl>
void
InstructionQueue<Impl>::switchOut()
{
    for (int i = 0; i < Impl::MaxFrameNum; i ++) {

        if (!instQueue[0][i].empty() || (numEntries != freeEntries) ||
            !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
            dumpInsts();
            assert(0);
        }
    }

    resetState();
    regDepGraph.reset();
    instsToExecute.clear();
    switchedOut = true;

    for (ThreadID tid = 0; tid < numThreads; ++tid) {
        memDepUnit[tid].switchOut();
    }

}

template <class Impl>
void
InstructionQueue<Impl>::takeOverFrom()
{
    switchedOut = false;
}

template <class Impl>
int
InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
{
    if (iqPolicy == Partitioned) {
        return numEntries / num_threads;
    } else {
        return 0;
    }
}

template <class Impl>
void
InstructionQueue<Impl>::resetEntries()
{
    if (iqPolicy != Dynamic || numThreads > 1) {
        int active_threads = activeThreads->size();

        list<ThreadID>::iterator threads = activeThreads->begin();
        list<ThreadID>::iterator end = activeThreads->end();

        while (threads != end) {
            ThreadID tid = *threads++;

            if (iqPolicy == Partitioned) {
                maxEntries[tid] = numEntries / active_threads;
            } else if(iqPolicy == Threshold && active_threads == 1) {
                maxEntries[tid] = numEntries;
            }
        }
    }
}

template <class Impl>
unsigned
InstructionQueue<Impl>::numFreeEntries()
{
    return freeEntries;
}

template <class Impl>
unsigned
InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
{
    return maxEntries[tid] - count[tid];
}

// Might want to do something more complex if it knows how many instructions
// will be issued this cycle.
template <class Impl>
bool
InstructionQueue<Impl>::isFull()
{
    if (freeEntries == 0) {
        return(true);
    } else {
        return(false);
    }
}

template <class Impl>
bool
InstructionQueue<Impl>::isFull(ThreadID tid)
{
    if (numFreeEntries(tid) == 0) {
        return(true);
    } else {
        return(false);
    }
}

template <class Impl>
bool
InstructionQueue<Impl>::hasReadyInsts()
{
    if (!listOrder.empty()) {
        return true;
    }

    for (int i = 0; i < Num_OpClasses; ++i) {
        if (!readyInsts[i].empty()) {
            return true;
        }
    }

    return false;
}

template <class Impl>
void
InstructionQueue<Impl>::insert(DynInstPtr &new_inst, int position)
{
    // Make sure the instruction is valid
    assert(new_inst);

    ThreadID tid = new_inst->threadNumber;
    int frame_id = new_inst->getFrameID();

    if (frameRecordBoard[tid][frame_id] == 0) {
        frameRecordBoard[tid][frame_id] = new_inst->getBlockID();
    }

    assert(frameRecordBoard[tid][frame_id] == new_inst->getBlockID());
    assert(freeEntries != 0);

    DPRINTF(EdgeIQ, "Adding instruction [Bid:%lli][Iid:%lli] @PC %#x to"
            " IQ[tid:%i][Frame:%i]."
            " Inst has %i operands\n",
            new_inst->getBlockID(), new_inst->getInstID(),
            new_inst->readPC(),tid, frame_id,
            new_inst->getNumOperands());

    if (new_inst->isRead()) {

        assert(position < TheISA::HeaderSize);
        assert(!readQueue[tid][frame_id][position]);

        readQueue[tid][frame_id][position] = new_inst;

        DPRINTF(EdgeIQ, "Reg Read inst encountered,"
                " add it to readQueue.\n" );

        // Set reg-read inst to reg dep graph as dependents.
        addToDependents(new_inst);

        iqReadsAdded++;
    } else if (new_inst->isWrite()) {

        assert(position < TheISA::HeaderSize);
        assert(!writeQueue[tid][frame_id][position]);

        DPRINTF(EdgeIQ, "Reg Write inst encountered,"
                " add it to write queue.\n");

        writeQueue[tid][frame_id][position] = new_inst;

        // Add reg-write inst to register dep graph as producer.
        addToProducers(new_inst);

        iqWritesAdded++;
    } else {

        assert(position < TheISA::MaxInstsInBlock);
        assert(!instQueue[tid][frame_id][position]);

        instQueue[tid][frame_id][position] = new_inst;

        // If we are a perfect predication instQueue, we need to set
        // the predication status here.
        if (isPerfectPredication) {
            TheISA::Predication inst_pred =
                new_inst->staticInst->getPredication();

            if (inst_pred == TheISA::PredUponTrue ||
                inst_pred == TheISA::PredUponFalse) {

                if (new_inst->getPreExePredStatus()) {

                    new_inst->setPredStatusValid();
                    new_inst->setPredMatched();

                    iqCorrectPredPredication++;
                }
            }
        }

        if (new_inst->getNumOperands() == 0 &&
            (!new_inst->isNop()) &&
            (new_inst->staticInst->getPredication() == TheISA::Disable ||
            new_inst->staticInst->getPredication() == TheISA::Reserved ||
            new_inst->isPredMatched())) {

            DPRINTF(EdgeIQ, "Inst need no operand, mark it as ready.\n");

            new_inst->setCanIssue();
        }

        // IQ count dont take heads (read/write) into consideration.
        --freeEntries;

        ++iqInstsAdded;

        count[tid]++;

        assert(freeEntries == (numEntries - countInsts()));
    }

    new_inst->setInIQ();

    if (new_inst->isMemRef()) {

        DPRINTF(EdgeIQ, "Mem ref inst encounted, dependent will"
                " be built later.\n" );

    } else {
        // Check to see if this inst can issue.
        addIfReady(new_inst);
    }
}

template<class Impl>
void
InstructionQueue<Impl>::buildMemDependent(DynInstPtr &mem_inst)
{
    assert(mem_inst->isMemRef());

    memDepUnit[mem_inst->threadNumber].insert(mem_inst);
}

template <class Impl>
void
InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
{
    // @todo:There's no non speculative insts right now ...
    panic("Unimplemented func: insertNonSpec(). \n");
}

template <class Impl>
void
InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
{
    // @todo:Don't know how to implemented barrier right now.
    panic("Unimplemented func: insertBarrier. \n");
}

template <class Impl>
typename Impl::DynInstPtr
InstructionQueue<Impl>::getInstToExecute()
{
    assert(!instsToExecute.empty());
    DynInstPtr inst = instsToExecute.front();
    instsToExecute.pop_front();
    return inst;
}

template <class Impl>
void
InstructionQueue<Impl>::addToOrderList(OpClass op_class)
{
    assert(!readyInsts[op_class].empty());

    ListOrderEntry queue_entry;

    queue_entry.queueType = op_class;

    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;

    ListOrderIt list_it = listOrder.begin();
    ListOrderIt list_end_it = listOrder.end();

    while (list_it != list_end_it) {
        if ((*list_it).oldestInst > queue_entry.oldestInst) {
            break;
        }

        list_it++;
    }

    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
    queueOnList[op_class] = true;
}

template <class Impl>
void
InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
{
    // Get iterator of next item on the list
    // Delete the original iterator
    // Determine if the next item is either the end of the list or younger
    // than the new instruction.  If so, then add in a new iterator right here.
    // If not, then move along.
    ListOrderEntry queue_entry;
    OpClass op_class = (*list_order_it).queueType;
    ListOrderIt next_it = list_order_it;

    ++next_it;

    queue_entry.queueType = op_class;
    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;

    while (next_it != listOrder.end() &&
           (*next_it).oldestInst < queue_entry.oldestInst) {
        ++next_it;
    }

    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
}

template <class Impl>
void
InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
{
    DPRINTF(EdgeIQ, "Processing FU completion [Bid:%lli][Iid:%lli]\n",
            inst->getBlockID(),
            inst->getInstID());

    // The CPU could have been sleeping until this op completed (*extremely*
    // long latency op).  Wake it if it was.  This may be overkill.

    // If block of some insts have completed, we should just return.
    if (isSwitchedOut() || inst->isBlockCompleted()) {

        DPRINTF(EdgeIQ, "FU completion not processed, "
                "IQ is switched out or block has completed [sn:%lli]\n",
                inst->seqNum);

        // If block of this inst completed and there's a fu-unit used, free it
        if (inst->isBlockCompleted() && fu_idx > -1) {
            fuPool->freeUnitNextCycle(fu_idx);
        }

        return;
    }

    executeStage->wakeCPU();

    if (fu_idx > -1)
        fuPool->freeUnitNextCycle(fu_idx);

    // @todo: Ensure that these FU Completions happen at the beginning
    // of a cycle, otherwise they could add too many instructions to
    // the queue.
    issueToExecuteQueue->access(-1)->size++;
    instsToExecute.push_back(inst);
}

// @todo: Figure out a better way to remove the squashed items from the
// lists.  Checking the top item of each list to see if it's squashed
// wastes time and forces jumps.
template <class Impl>
void
InstructionQueue<Impl>::scheduleReadyInsts()
{
    DPRINTF(EdgeIQ, "Attempting to schedule ready instructions from "
            "the IQ.\n");

    Issue2Execute *i2e_info = issueToExecuteQueue->access(0);

    // Have iterator to head of the list
    // While I haven't exceeded bandwidth or reached the end of the list,
    // Try to get a FU that can do what this op needs.
    // If successful, change the oldestInst to the new top of the list, put
    // the queue in the proper place in the list.
    // Increment the iterator.
    // This will avoid trying to schedule a certain op class if there are no
    // FUs that handle it.
    ListOrderIt order_it = listOrder.begin();
    ListOrderIt order_end_it = listOrder.end();
    int total_issued = 0;

    while (total_issued < totalWidth &&
           executeStage->canIssue() &&
           order_it != order_end_it) {
        OpClass op_class = (*order_it).queueType;

        assert(!readyInsts[op_class].empty());

        DynInstPtr issuing_inst = readyInsts[op_class].top();

        assert(issuing_inst->seqNum == (*order_it).oldestInst);

        if (issuing_inst->isSquashed() || issuing_inst->isBlockCompleted()) {

            DPRINTF(EdgeIQ, "Inst[Bid:%lli][Iid:%lli] squashed"
                    " or block completed, can't issue!\n",
                    issuing_inst->getBlockID(),
                    issuing_inst->getInstID());

            readyInsts[op_class].pop();

            if (!readyInsts[op_class].empty()) {
                moveToYoungerInst(order_it);
            } else {
                readyIt[op_class] = listOrder.end();
                queueOnList[op_class] = false;
            }

            listOrder.erase(order_it++);

            ++iqDummyInstsIssued;

            continue;
        }

        int idx = -2;
        int op_latency = 1;
        ThreadID tid = issuing_inst->threadNumber;

        if (op_class != No_OpClass) {
            idx = fuPool->getUnit(op_class);

            if (idx > -1) {
                op_latency = fuPool->getOpLatency(op_class);
            }
        }

        // If we have an instruction that doesn't require a FU, or a
        // valid FU, then schedule for execution.
        if (idx == -2 || idx != -1) {
            if (op_latency == 1) {
                i2e_info->size++;
                instsToExecute.push_back(issuing_inst);

                // Add the FU onto the list of FU's to be freed next
                // cycle if we used one.
                if (idx >= 0)
                    fuPool->freeUnitNextCycle(idx);
            } else {
                int issue_latency = fuPool->getIssueLatency(op_class);
                // Generate completion event for the FU
                FUCompletion *execution = new FUCompletion(issuing_inst,
                                                           idx, this);

                cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1));

                // @todo: Enforce that issue_latency == 1 or op_latency
                if (issue_latency > 1) {
                    // If FU isn't pipelined, then it must be freed
                    // upon the execution completing.
                    execution->setFreeFU();
                } else {
                    // Add the FU onto the list of FU's to be freed next cycle.
                    fuPool->freeUnitNextCycle(idx);
                }
            }

            DPRINTF(EdgeIQ, "Thread %i: Issuing instruction PC %#x "
                    "[sn:%lli]\n",
                    tid, issuing_inst->readPC(),
                    issuing_inst->seqNum);

            readyInsts[op_class].pop();

            if (!readyInsts[op_class].empty()) {
                moveToYoungerInst(order_it);
            } else {
                readyIt[op_class] = listOrder.end();
                queueOnList[op_class] = false;
            }

            issuing_inst->setIssued();
            ++total_issued;

            if (!issuing_inst->isMemRef()) {
                DPRINTF(EdgeIQ, "Issuing none mem insts.\n");
            } else {
                DPRINTF(EdgeIQ, "Issuing mem insts.\n");
            }

            listOrder.erase(order_it++);
            statIssuedInstType[tid][op_class]++;

            // Only reg-write need to mark the wboutstanding variable.
            if (issuing_inst->isWrite()) {
                DPRINTF(EdgeIQ, "Issuing reg-write inst.\n");
                executeStage->incrWb(issuing_inst->seqNum);
            } else if (issuing_inst->isRead()) {
                DPRINTF(EdgeIQ, "Issuing reg-read inst.\n");
            }

        } else {
            statFuBusy[op_class]++;
            fuBusy[tid]++;
            ++order_it;
        }
    }

    numIssuedDist.sample(total_issued);
    iqInstsIssued += total_issued;

    // If we issued any instructions, tell the CPU we had activity.
    if (total_issued) {
        cpu->activityThisCycle();
    } else {
        DPRINTF(EdgeIQ, "Not able to schedule any instructions.\n");
    }
}

template <class Impl>
void
InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
{
    panic("Unimplemented function: shceduleNonSpec.\n");
}

template <class Impl>
void
InstructionQueue<Impl>::commit(const TheISA::BlockID &commit_bid, ThreadID tid)
{
    DPRINTF(EdgeIQ, "[tid:%i]: Committing inst block older than [Bid:%i]\n",
            tid,commit_bid);

    int commit_count = 0;

    for (int idx = 0; idx < Impl::MaxFrameNum; idx++) {
        if (frameRecordBoard[tid][idx] <= commit_bid &&
            frameRecordBoard[tid][idx] != 0) {

            DPRINTF(EdgeIQ, "Inst in frame[%i] with Bid[%lli] committed.\n",
                    idx, frameRecordBoard[tid][idx]);

            QueueIt iq_it = instQueue[tid][idx].begin();
            QueueIt iq_end = instQueue[tid][idx].end();

            while (iq_it != iq_end) {
                if ((*iq_it)) {
                    (*iq_it) = NULL;
                    commit_count++;
                }
                ++iq_it;
            }

            // Free entries dont take heads (read/write) into
            // consideration.
            freeEntries += commit_count;
            count[tid] -= commit_count;

            QueueIt rd_it = readQueue[tid][idx].begin();
            QueueIt rd_end = readQueue[tid][idx].end();

            while (rd_it != rd_end) {
                if ((*rd_it)) {
                    (*rd_it) = NULL;
                }
                ++rd_it;
            }

            QueueIt wr_it = writeQueue[tid][idx].begin();
            QueueIt wr_end = writeQueue[tid][idx].end();

            while (wr_it != wr_end) {
                if ((*wr_it)) {
                    (*wr_it) = NULL;
                }
                ++wr_it;
            }

            // Because this block is committed, so clear the record
            // board.
            frameRecordBoard[tid][idx] = 0;
        }
    }

    assert(freeEntries == (numEntries - countInsts()));
}

template <class Impl>
void
InstructionQueue<Impl>::complete(EdgeBlockPtr & inst_block)
{
    int frame_id = inst_block->getFrameID();
    ThreadID tid = inst_block->getTid();

    assert(frameRecordBoard[tid][frame_id]
           == inst_block->getBlockID());

    // We need to mark all the insts in inst queue as block completed
    // to avoid scheduling inst when block completion condition has been
    // satisfied. Here we should only mark inst having exactly the
    // wanted block id to be compeleted.
    DPRINTF(EdgeIQ, "[tid:%i]: Completing inst block [Bid:%i][Frame:%i]."
             " Mark insts of this block as block completed. \n",
            tid,
            inst_block->getBlockID(),
            frame_id);

    QueueIt iq_it = instQueue[tid][frame_id].begin();
    QueueIt iq_end = instQueue[tid][frame_id].end();

    while (iq_it != iq_end) {

        if ((*iq_it)) {

            assert((*iq_it)->getBlockID() == inst_block->getBlockID());

            (*iq_it)->setBlockCompleted();
        }
        ++iq_it;
    }

    QueueIt rd_it = readQueue[tid][frame_id].begin();
    QueueIt rd_end = readQueue[tid][frame_id].end();

    while (rd_it != rd_end) {

        if ((*rd_it)) {

            assert((*rd_it)->getBlockID() == inst_block->getBlockID());

            (*rd_it)->setBlockCompleted();
        }
        ++rd_it;
    }

    QueueIt wr_it = writeQueue[tid][frame_id].begin();
    QueueIt wr_end = writeQueue[tid][frame_id].end();

    while (wr_it != wr_end) {

        if ((*wr_it)) {

            assert((*wr_it)->getBlockID() == inst_block->getBlockID());

            (*wr_it)->setBlockCompleted();
        }
        ++wr_it;
    }
}

template<class Impl>
void
InstructionQueue<Impl>::completeInRegDepGraph(DynInstPtr & inst)
{
    assert(inst->isWrite());
    regDepGraph.complete(inst->getMappedDestReg(0), inst);
}

template<class Impl>
void
InstructionQueue<Impl>::writeBack(TheISA::BlockID wb_block_id, ThreadID tid)
{
    DPRINTF(EdgeIQ, "[tid:%i]: Write back inst block older than [Bid:%i]\n",
            tid, wb_block_id);

    for (int idx = 0; idx < Impl::MaxFrameNum; idx++) {

        if (frameRecordBoard[tid][idx] <= wb_block_id &&
            frameRecordBoard[tid][idx] != 0) {

            QueueIt wr_it = writeQueue[tid][idx].begin();
            QueueIt wr_end = writeQueue[tid][idx].end();

            while (wr_it != wr_end) {

                DynInstPtr write_inst = (*wr_it);

                // Ignore NOPS
                if (!write_inst) {
                    ++wr_it;
                    continue;
                }

                assert(write_inst->isExecuted());

                if (!write_inst->isNullified()) {

                    // This will write register.
                    write_inst->execute();

                    DPRINTF(EdgeIQ, "Write back to reg[%i] by"
                            " inst[Bid:%lli][Iid:%lli].\n",
                            write_inst->getMappedDestReg(0),
                            write_inst->getBlockID(),
                            write_inst->getInstID());

                    // Nullified inst should be committed when it was nullified.
                    regDepGraph.commit(write_inst->getMappedDestReg(0),write_inst);

                    iqRegWriteWrited++;
                } else {
                    DPRINTF(EdgeIQ, "Nullified reg-write inst[Bid:%lli][Iid:%lli]\n",
                            write_inst->getBlockID(), write_inst->getInstID() );
                }

                executeStage->decrWb(write_inst->seqNum);

                ++wr_it;
            }
        }
    }
}

template <class Impl>
int
InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
{
    int dependents = 0;

    DPRINTF(EdgeIQ, "Waking dependents of completed"
            " instruction[Bid:%lli][Iid:%lli].\n",
            completed_inst->getBlockID(), 
            completed_inst->getInstID() );

    // Dump exec trace
    if (completed_inst->traceData) {
        completed_inst->traceData->dump();
        delete completed_inst->traceData;
        completed_inst->traceData = NULL;
    }

    assert(!completed_inst->isSquashed());

    ThreadID tid = completed_inst->threadNumber;
    int frame_id = completed_inst->getFrameID();

    // Tell the memory dependence unit to wake any dependents on this
    // instruction if it is a memory instruction.  Also complete the memory
    // instruction at this point since we know it executed without issues.
    // @todo: Might want to rename "completeMemInst" to something
    // indicating that it won't need to be replayed, and call this
    // earlier.  Might not be a big deal.

    // No matter whether the mem insts have been nullified or not,
    // they should always wake up dependence in memDepUnit.
    if (completed_inst->isMemRef()) {
        memDepUnit[tid].wakeDependents(completed_inst);
        completeMemInst(completed_inst);
    }

    DynInstPtr consumer;
    OpSize result = 0;

    for (int consumer_idx = 0;
         consumer_idx < completed_inst->getNumConsumers();
         consumer_idx ++)
    {
        dependents ++;

        // Insts with predication slot may received 
        // multiple predications among which only
        // one is matched. If there is a false 
        // predication received, we should avoid
        // add this inst into ready list if the inst
        // has been added before.
        bool add_to_ready_list = true;

        uint8_t type =
            completed_inst->getConsumerType(consumer_idx);

        DPRINTF(EdgeIQ, "Waking any dependents on consumer[idx:%i][type:%i][id:%i]"
                "in frame[%i].\n",
                (int)consumer_idx,
                (int)completed_inst->getConsumerType(consumer_idx),
                (int)completed_inst->getConsumerID(consumer_idx),
                frame_id);

        if (type == TheISA::WriteSlotOrNoTarget) {

            uint8_t sub_type =
                completed_inst->getConsumerSubType(consumer_idx);

            if (sub_type == TheISA::WriteSlot) {

               // Wakeup write inst
               consumer = writeQueue[tid][frame_id]\
                          [completed_inst->getConsumerID(consumer_idx)];

               assert(consumer);
               assert(consumer->isWrite());

               // Operand of write-reg inst is defaulted to 0
               consumer->setIntOperand(0,
                                       completed_inst->getIntResult() );
               // Mark inst as receiving a operand
               consumer->markOperandReady();

            } else {
                // No target, continue.
                continue;
            }

        } else if (type == TheISA::PredSlot) {

            // Wakeup insts.
            consumer = instQueue[tid][frame_id]\
                                [completed_inst->getConsumerID(consumer_idx)];
            assert(consumer);

            uint64_t data = completed_inst->getIntResult();
              
            // If an exception token is combined with 
            // a predication, the predicate value should 
            // always be set as false.
            if (completed_inst->getDataflowTokenType()
                == TheISA::Exception) {
                data = 0;
            }
            
            if (data == 0) {
                add_to_ready_list = 
                    consumer->setPredStatus(TheISA::PredFalse);
            } else {
                add_to_ready_list = 
                    consumer->setPredStatus(TheISA::PredTrue);
            }

            // Mark inst as receiving a predication
            consumer->markPredReady();

            iqPredicationPropagated ++;
        } else {

            assert(type == TheISA::Operand0 || type == TheISA::Operand1);

            result = completed_inst->getIntResult();
            consumer = instQueue[tid][frame_id]\
                                [completed_inst->getConsumerID(consumer_idx)];

            if (type == TheISA::Operand0) {
                consumer->setIntOperand(0, result);
            } else if (type == TheISA::Operand1){
                consumer->setIntOperand(1, result);
            } else {
                panic("Unrecogonized operand number\n");
            }
            // Mark inst as receiving a operand
            consumer->markOperandReady();
        }

        iqOperandsPropagated++;

        DPRINTF(EdgeIQ, "Consumer[Bid:%lli][Iid:%lli].\n",
                consumer->getBlockID(),
                consumer->getInstID());

        // Producer and consumer should be in the same inst block.
        assert(completed_inst->getBlockID() == consumer->getBlockID());

        // Read register is the head of a inst block, so it
        // has no token to propagate.
        if (!completed_inst->isRead()) {
            // If the data flow token type of this producer is Nullification,
                // set the consumer to be nullified. Propagating the token.
            if (completed_inst->getDataflowTokenType()
                        == TheISA::Nullification ) {

                DPRINTF( EdgeIQ, "Nullify consumer[Bid:%lli][Iid:%lli] @PC %lli",
                    consumer->getBlockID(),
                    consumer->getInstID(),
                    consumer->readPC() );

                //assert(type != TheISA::PredSlot);
                // If a null token is combined with
                // the predication, this null token
                // will be completely ignored.
                if (type != TheISA::PredSlot) {
                    consumer->setNullified();
                    consumer->setDataflowTokenType(TheISA::Nullification);

                    iqNullTokenPropagated ++;
                }

            } else if (completed_inst->getDataflowTokenType()
                        == TheISA::Exception) {

                Fault fault = completed_inst->getFault();

                assert(fault!=NoFault);

                DPRINTF(EdgeIQ, "Propagate fault %s from"
                        " producer[Bid%lli][Iid%lli] to consumer[Bid%lli][Iid%lli].\n",
                        fault->name(), 
                        completed_inst->getBlockID(),
                        completed_inst->getInstID(),
                        consumer->getBlockID(), 
                        consumer->getInstID() );

                consumer->fault = fault;
                //Propagate the fault
                consumer->setDataflowTokenType ( TheISA::Exception );
                iqExceptTokenPropagated ++;
            }
        }

        DPRINTF(EdgeIQ, "Inst ID of consumer inst is %lli "
                "while Consumer ID of complete inst is %lli\n",
                consumer->getInstID(),
                completed_inst->getConsumerID( consumer_idx ) );

        // Check if this inst can be issued.
        if (add_to_ready_list) {
            addIfReady(consumer);
        }
    }

    return dependents;
}

template <class Impl>
void
InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
{
    OpClass op_class = ready_inst->opClass();

    readyInsts[op_class].push(ready_inst);

    // Will need to reorder the list if either a queue is not on the list,
    // or it has an older instruction than last time.
    if (!queueOnList[op_class]) {
        addToOrderList(op_class);
    } else if (readyInsts[op_class].top()->seqNum  <
               (*readyIt[op_class]).oldestInst) {
        listOrder.erase(readyIt[op_class]);
        addToOrderList(op_class);
    }

    DPRINTF(EdgeIQ, "Instruction is ready to issue, putting it onto "
            "the ready list, PC %#x opclass:%i [Bid:%lli][Iid:%lli].\n",
            ready_inst->readPC(),
            op_class,
            ready_inst->getBlockID(),
            ready_inst->getInstID());
}

template <class Impl>
void
InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
{
    DPRINTF(EdgeIQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);

    resched_inst->clearCanIssue();

    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
}

template <class Impl>
void
InstructionQueue<Impl>::replayMemInst(ThreadID tid)
{
    memDepUnit[tid].replay();
}

template <class Impl>
void
InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
{
    ThreadID tid = completed_inst->threadNumber;

    DPRINTF(EdgeIQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
            completed_inst->readPC(), completed_inst->seqNum);

    completed_inst->memOpDone = true;

    memDepUnit[tid].completed(completed_inst);
}

template <class Impl>
void
InstructionQueue<Impl>::violation(DynInstPtr &store,
                                  DynInstPtr &faulting_load)
{
    memDepUnit[store->threadNumber].violation(store, faulting_load);
}

template <class Impl>
void
InstructionQueue<Impl>::squash(ThreadID tid)
{
    DPRINTF(EdgeIQ, "[tid:%i]: Starting to squash insts in "
            "the IQ.\n", tid);

    // Read instruction sequence number of last instruction out of the
    // time buffer.
    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneBlockID;

    // Call doSquash if there are insts in the IQ
    if (count[tid] > 0) {
        doSquash(tid);
    }

    // Also tell the memory dependence unit to squash.
    memDepUnit[tid].squash(squashedSeqNum[tid], tid);

}

template <class Impl>
void
InstructionQueue<Impl>::doSquash(ThreadID tid)
{
    // Squashing will clean up all the insts younger than
    // squashedSeqNum[tid]

    DPRINTF(EdgeIQ, "[tid:%i]: Squashing until block id %i!\n",
            tid, squashedSeqNum[tid]);

    TheISA::BlockID squashed_id = squashedSeqNum[tid];

    for (int idx = 0; idx < Impl::MaxFrameNum; idx++) {

        if (frameRecordBoard[tid][idx] > squashed_id) {

            QueueIt wr_it = writeQueue[tid][idx].begin();
            QueueIt wr_end = writeQueue[tid][idx].end();

            while (wr_it != wr_end) {

                DynInstPtr squashed_write = (*wr_it);

                if (squashed_write) {

                    DPRINTF(EdgeIQ, "[tid:%i]: Squashing write[Iid:%i]"
                            " PC %#x of Block[Bid:%lli]"
                            "squashed. Issued flag = %d.\n",
                            tid, squashed_write->getInstID(), 
                            squashed_write->readPC(),
                            squashed_write->getBlockID(), 
                            squashed_write->isIssued());

                    if (squashed_write->isIssued() ) {
                        executeStage->decrWb(squashed_write->seqNum);
                    }

                    // Clear dependence in reg dep graph.
                    regDepGraph.remove(squashed_write->getMappedDestReg(0), 
                                       squashedSeqNum[tid]);

                    // Mark it as squashed within the IQ.
                    squashed_write->setSquashedInIQ();

                    // @todo: Remove this hack where several statuses are set so the
                    // inst will flow through the rest of the pipeline.
                    squashed_write->setIssued();
                    squashed_write->setCanCommit();
                    squashed_write->clearInIQ();

                    (*wr_it) = NULL;
                }
                ++wr_it;
            }

            QueueIt rd_it = readQueue[tid][idx].begin();
            QueueIt rd_end = readQueue[tid][idx].end();

            while (rd_it != rd_end) {

                DynInstPtr squashed_read = (*rd_it);

                if (squashed_read) {

                    DPRINTF(EdgeIQ, "[tid:%i]: Squashing read[Iid:%i]"
                            " PC %#x of Block[Bid:%lli]"
                            "squashed. Issued flag = %d.\n",
                            tid, squashed_read->getInstID(),
                            squashed_read->readPC(),
                            squashed_read->getBlockID(),
                            squashed_read->isIssued());

                    // Mark it as squashed within the IQ.
                    squashed_read->setSquashedInIQ();

                    // @todo: Remove this hack where several statuses are set so the
                    // inst will flow through the rest of the pipeline.
                    squashed_read->setIssued();
                    squashed_read->setCanCommit();
                    squashed_read->clearInIQ();

                    (*rd_it) = NULL;
                }
                ++rd_it;
            }

            QueueIt iq_it = instQueue[tid][idx].begin();
            QueueIt iq_end = instQueue[tid][idx].end();

            while (iq_it != iq_end) {

                DynInstPtr squashed_inst = (*iq_it);

                if (squashed_inst) {
                    // Squash anything that matched the block id.
                    DPRINTF(EdgeIQ, "[tid:%i]: Instruction [Iid:%lli] PC %#x"
                            " of Block[Bid:%lli]"
                            "squashed in frame[%i].\n",
                            tid, squashed_inst->getInstID(),
                            squashed_inst->readPC(),
                            squashed_inst->getBlockID(),
                            idx);

                    // Mark it as squashed within the IQ.
                    squashed_inst->setSquashedInIQ();

                    // @todo: Remove this hack where several statuses are set so the
                    // inst will flow through the rest of the pipeline.
                    squashed_inst->setIssued();
                    squashed_inst->setCanCommit();
                    squashed_inst->clearInIQ();

                    //Update Thread IQ Count
                    count[tid]--;
                    ++freeEntries;
                    ++iqInstsSquashed;

                    (*iq_it) = NULL;
                }
                ++iq_it;
            }

            // Clear this entry.
            frameRecordBoard[tid][idx] = 0;
        }
    }
}

template <class Impl>
bool
InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
{
    // Only reg read inst can be added into dependent graph
    // and only one src reg is allowed.
    assert(new_inst->isRead());
    assert(new_inst->numSrcRegs() == 1);

    bool return_val = false;

    // Only add it to the dependency graph if
    // source register is not ready.
    PhysRegIndex src_reg = new_inst->getMappedSrcReg(0);
    if (src_reg < numPhysRegs) {
        // Try to add reg-read inst into reg dep graph.
        // Return true means this inst can issue immediately
        // while return false means this inst has been added
        // into reg dep graph.
        if (!regDepGraph.insertConsumer(src_reg, new_inst)){
            DPRINTF(EdgeIQ, "Instruction PC %#x has src reg %i that "
                    "is being added to the dependency chain.\n",
                    new_inst->readPC(), src_reg);

            // Change the return value to indicate that something
            // was added to the dependency graph.
            return_val = true;

            iqRegReadDep ++;
        } else {
            DPRINTF(EdgeIQ, "Register Read Inst[Bid:%lli][Iid:%lli] @PC %#x"
                    " has src reg %i that "
                    "became ready before it reached the IQ.\n",
                    new_inst->getBlockID(),
                    new_inst->getInstID(),
                    new_inst->readPC(), src_reg);
            // Mark this register read inst as can-issue.
            new_inst->setCanIssue();
        }
    }else {
        DPRINTF(EdgeIQ, "Not a general register, leave it alone.\n");
    }
    return return_val;
}

template <class Impl>
void
InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
{
    // A ptr to the producing instruction will be placed
    // in the head node of the dependency links.

    // Only write register inst is supporsed to arrive here
    // and only one dest reg is allowed.
    assert(new_inst->isWrite());
    assert(new_inst->numDestRegs() == 1);

    PhysRegIndex dest_reg = new_inst->getMappedDestReg(0);

    if (dest_reg < numPhysRegs) {
        // Set entry of this dest reg.
        regDepGraph.insertProducer(dest_reg, new_inst);
    } else {
        DPRINTF(EdgeIQ, "Not a general register, leave it alone.\n");
    }
}

template <class Impl>
void
InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
{
    // If the instruction now has all of its source registers
    // available, then add it to the list of ready instructions.

    if (!inst->readyToIssue()) {
        DPRINTF(EdgeIQ,"Instruction %d[Iid:%i] still has %d src.\n",
                inst->seqNum,inst->getInstID(),
                inst->getReadyOperands());

        DPRINTF(EdgeIQ,"Instruction is %s.\n",
                inst->staticInst->disassemble(inst->readPC()));
    }

    if (inst->readyToIssue()) {

        DPRINTF(EdgeIQ,"Inst[Bid:%lli][Iid:%lli] is ready to issue\n"
                "Inst %s.\n", inst->getBlockID(), inst->getInstID(),
                inst->staticInst->disassemble(inst->readPC()));

        if (inst->isMemRef()) {

            DPRINTF(EdgeIQ, "This is a memory ref inst, checking if "
                    "memory instruction can issue.\n");

            // Message to the mem dependence unit that this instruction has
            // its registers ready.
            memDepUnit[inst->threadNumber].opsReady(inst);

            return;
        }

        OpClass op_class = inst->opClass();

        DPRINTF(EdgeIQ, "Putting instruction onto "
                "the ready list, PC %#x opclass:%i [Bid:%lli][Iid:%lli].\n",
                inst->readPC(), op_class,
                inst->getBlockID(), inst->getInstID());

        readyInsts[op_class].push(inst);

        // Will need to reorder the list if either a queue is not on the list,
        // or it has an older instruction than last time.
        if (!queueOnList[op_class]) {
            addToOrderList(op_class);
        } else if (readyInsts[op_class].top()->seqNum  <
                   (*readyIt[op_class]).oldestInst) {
            listOrder.erase(readyIt[op_class]);
            addToOrderList(op_class);
        }
    }
}

template <class Impl>
int
InstructionQueue<Impl>::countInsts()
{
    // @todo: This is really simple ... 
    return numEntries - freeEntries;
}

template <class Impl>
void
InstructionQueue<Impl>::dumpLists()
{
    panic("Unimplemented func: dumpLists().\n");
}

template <class Impl>
void
InstructionQueue<Impl>::dumpInsts()
{
    panic("Unimplemented func: dumpInsts().\n");
}
